&soc {
	pil_gpu: qcom,kgsl-hyp {
		compatible = "qcom,pil-tz-generic";
		qcom,pas-id = <13>;
		qcom,firmware-name = "a620_zap";
	};

	msm_bus: qcom,kgsl-busmon {
		label = "kgsl-busmon";
		compatible = "qcom,kgsl-busmon";
		operating-points-v2 = <&gpu_opp_table>;
	};

	gpubw: qcom,gpubw {
		compatible = "qcom,devbw";
		governor = "bw_vbif";
		qcom,src-dst-ports = <26 512>;
		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
	};

	gpu_opp_table: gpu-opp-table {
		compatible = "operating-points-v2";

		opp-750000000 {
			opp-hz = /bits/ 64 <750000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
		};

		opp-700000000 {
			opp-hz = /bits/ 64 <700000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;
		};

		opp-670000000 {
			opp-hz = /bits/ 64 <670000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;
		};

		opp-625000000 {
			opp-hz = /bits/ 64 <625000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
		};

		opp-540000000 {
			opp-hz = /bits/ 64 <540000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
		};

		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
		};

		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
		};

		opp-275000000 {
			opp-hz = /bits/ 64 <275000000>;
			opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
		};
	};

	msm_gpu: qcom,kgsl-3d0@3d00000 {
		label = "kgsl-3d0";
		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
		status = "ok";
		reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
			<0x3de0000 0x1000>, <0x3d8b000 0x2000>;
		reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
				"isense_cntl";
		interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "kgsl_3d0_irq";
		qcom,id = <0>;

		qcom,chipid = <0x06020000>;

		qcom,initial-pwrlevel = <3>;

		qcom,idle-timeout = <80>; /* msecs */

		qcom,highest-bank-bit = <14>;

		qcom,min-access-length = <32>;

		qcom,ubwc-mode = <3>;
		qcom,no-nap;
		qcom,snapshot-size = <2048576>; /* bytes */
		qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */

		#cooling-cells = <2>;
		qcom,tzone-name = "gpuss-max-step";

		/* CPU latency parameter */
		qcom,pm-qos-active-latency = <67>;
		qcom,pm-qos-wakeup-latency = <67>;

		/* Enable context aware freq. scaling */
		qcom,enable-ca-jump;
		/* Context aware jump busy penalty in us */
		qcom,ca-busy-penalty = <12000>;

		clocks = <&gpucc GPU_CC_CXO_CLK>,
			<&gcc GCC_DDRSS_GPU_AXI_CLK>,
			<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
			<&gpucc GPU_CC_CX_GMU_CLK>,
			<&gpucc GPU_CC_AHB_CLK>,
			<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;

		clock-names = "rbbmtimer_clk", "mem_clk",
				"mem_iface_clk", "gmu_clk",
				"gpu_cc_ahb", "smmu_vote";

		qcom,gpubw-dev = <&gpubw>;
		qcom,bus-control;
		qcom,msm-bus,name = "grp3d";
		qcom,msm-bus,num-cases = <13>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
				<26 512 0 0>,
				<26 512 0 400000>,      /* 1 bus=100 */
				<26 512 0 800000>,      /* 2 bus=200 */
				<26 512 0 1200000>,     /* 3 bus=300 */
				<26 512 0 1804800>,     /* 4 bus=451 */
				<26 512 0 2188000>,     /* 5 bus=547 */
				<26 512 0 2724000>,     /* 6 bus=681 */
				<26 512 0 3072000>,     /* 7 bus=768 */
				<26 512 0 4068000>,     /* 8 bus=1017 */
				<26 512 0 5412000>,     /* 9 bus=1353 */
				<26 512 0 6220000>,     /* 10 bus=1555 */
				<26 512 0 7216000>,     /* 11 bus=1804 */
				<26 512 0 8371200>;     /* 12 bus=2092 */

		/* GDSC regulator names */
		regulator-names = "vddcx", "vdd";
		/* GDSC oxili regulators */
		vddcx-supply = <&gpu_cx_gdsc>;
		vdd-supply = <&gpu_gx_gdsc>;

		nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>, <&gpu_lm_efuse>;
		nvmem-cell-names = "speed_bin", "gaming_bin", "isense_slope";

		/* GPU OPP data */
		operating-points-v2 = <&gpu_opp_table>;

		/* GPU Mempools */
		qcom,gpu-mempools {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "qcom,gpu-mempools";

			/* 4K Page Pool configuration */
			qcom,gpu-mempool@0 {
				reg = <0>;
				qcom,mempool-page-size = <4096>;
				qcom,mempool-reserved = <2048>;
				qcom,mempool-allocate;
			};
			/* 8K Page Pool configuration */
			qcom,gpu-mempool@1 {
				reg = <1>;
				qcom,mempool-page-size = <8192>;
				qcom,mempool-reserved = <1024>;
				qcom,mempool-allocate;
			};
			/* 64K Page Pool configuration */
			qcom,gpu-mempool@2 {
				reg = <2>;
				qcom,mempool-page-size = <65536>;
				qcom,mempool-reserved = <256>;
			};
			/* 1M Page Pool configuration */
			qcom,gpu-mempool@3 {
				reg = <3>;
				qcom,mempool-page-size = <1048576>;
				qcom,mempool-reserved = <32>;
			};
		};

		/*
		 * Speed-bin zero is default speed bin.
		 * For rest of the speed bins, speed-bin value
		 * is calulated as FMAX/4.8 MHz round up to zero
		 * decimal places.
		 */
		qcom,gpu-pwrlevel-bins {
			#address-cells = <1>;
			#size-cells = <0>;

			compatible="qcom,gpu-pwrlevel-bins";

			qcom,gpu-pwrlevels-0 {
				#address-cells = <1>;
				#size-cells = <0>;

				qcom,speed-bin = <0>;
				qcom,ca-target-pwrlevel = <2>;
				qcom,initial-pwrlevel = <3>;

				/* NOM */
				qcom,gpu-pwrlevel@0 {
					reg = <0>;
					qcom,gpu-freq = <625000000>;
					qcom,bus-freq = <10>;
					qcom,bus-min = <9>;
					qcom,bus-max = <12>;
					qcom,acd-level = <0x802C5FFD>;
				};

				/* SVS L1 */
				qcom,gpu-pwrlevel@1 {
					reg = <1>;
					qcom,gpu-freq = <500000000>;
					qcom,bus-freq = <8>;
					qcom,bus-min = <7>;
					qcom,bus-max = <10>;
					qcom,acd-level = <0xA02C5FFD>;
				};

				/* SVS */
				qcom,gpu-pwrlevel@2 {
					reg = <2>;
					qcom,gpu-freq = <400000000>;
					qcom,bus-freq = <7>;
					qcom,bus-min = <5>;
					qcom,bus-max = <8>;
					qcom,acd-level = <0xA02C5FFD>;
				};

				/* Low SVS */
				qcom,gpu-pwrlevel@3 {
					reg = <3>;
					qcom,gpu-freq = <275000000>;
					qcom,bus-freq = <5>;
					qcom,bus-min = <5>;
					qcom,bus-max = <7>;
					qcom,acd-level = <0x802F5FFD>;
				};

				qcom,gpu-pwrlevel@4 {
					reg = <4>;
					qcom,gpu-freq = <0>;
					qcom,bus-freq = <0>;
					qcom,bus-min = <0>;
					qcom,bus-max = <0>;
				};
			};

			qcom,gpu-pwrlevels-1 {
				#address-cells = <1>;
				#size-cells = <0>;

				qcom,speed-bin = <132>;

				qcom,initial-pwrlevel = <3>;
				qcom,ca-target-pwrlevel = <2>;

				/* NOM */
				qcom,gpu-pwrlevel@0 {
					reg = <0>;
					qcom,gpu-freq = <625000000>;
					qcom,bus-freq = <10>;
					qcom,bus-min = <9>;
					qcom,bus-max = <12>;
					qcom,acd-level = <0x802C5FFD>;
				};

				/* SVS L1 */
				qcom,gpu-pwrlevel@1 {
					reg = <1>;
					qcom,gpu-freq = <500000000>;
					qcom,bus-freq = <8>;
					qcom,bus-min = <7>;
					qcom,bus-max = <10>;
					qcom,acd-level = <0xA02C5FFD>;
				};

				/* SVS */
				qcom,gpu-pwrlevel@2 {
					reg = <2>;
					qcom,gpu-freq = <400000000>;
					qcom,bus-freq = <7>;
					qcom,bus-min = <5>;
					qcom,bus-max = <8>;
					qcom,acd-level = <0xA02C5FFD>;
				};

				/* Low SVS */
				qcom,gpu-pwrlevel@3 {
					reg = <3>;
					qcom,gpu-freq = <275000000>;
					qcom,bus-freq = <5>;
					qcom,bus-min = <5>;
					qcom,bus-max = <7>;
					qcom,acd-level = <0x802F5FFD>;
				};

				qcom,gpu-pwrlevel@4 {
					reg = <4>;
					qcom,gpu-freq = <0>;
					qcom,bus-freq = <0>;
					qcom,bus-min = <0>;
					qcom,bus-max = <0>;
				};
			};

			qcom,gpu-pwrlevels-3 {
				#address-cells = <1>;
				#size-cells = <0>;

				qcom,speed-bin = <115>;
				qcom,initial-pwrlevel = <2>;
				qcom,ca-target-pwrlevel = <1>;

				/* SVS L1 */
				qcom,gpu-pwrlevel@0 {
					reg = <0>;
					qcom,gpu-freq = <540000000>;
					qcom,bus-freq = <8>;
					qcom,bus-min = <7>;
					qcom,bus-max = <12>;
					qcom,acd-level = <0x802C5FFD>;
				};

				/* SVS */
				qcom,gpu-pwrlevel@1 {
					reg = <1>;
					qcom,gpu-freq = <400000000>;
					qcom,bus-freq = <7>;
					qcom,bus-min = <5>;
					qcom,bus-max = <8>;
					qcom,acd-level = <0xA02C5FFD>;
				};

				/* Low SVS */
				qcom,gpu-pwrlevel@2 {
					reg = <2>;
					qcom,gpu-freq = <275000000>;
					qcom,bus-freq = <5>;
					qcom,bus-min = <5>;
					qcom,bus-max = <7>;
					qcom,acd-level = <0x802F5FFD>;
				};

				qcom,gpu-pwrlevel@3 {
					reg = <3>;
					qcom,gpu-freq = <0>;
					qcom,bus-freq = <0>;
					qcom,bus-min = <0>;
					qcom,bus-max = <0>;
				};
			};
		};

		qcom,cpu-to-gpu-cfg-path {
			qcom,msm-bus,name = "gpu_cfg";
			qcom,msm-bus,num-cases = <3>;
			qcom,msm-bus,num-paths = <1>;
			qcom,msm-bus,vectors-KBps =
				<1 598 0 0>,            // off
				<1 598 0 100>,          // min freq
				<1 598 0 9999999>;      // max freq
		};
	};

	kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
		compatible = "qcom,kgsl-smmu-v2";

		reg = <0x03da0000 0x10000>;
		/* CB5(ATOS) & CB5/6/7 are protected by HYP */
		qcom,protect = <0xa0000 0xc000>;

		clocks =<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
			<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
			<&gpucc GPU_CC_AHB_CLK>,
			<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;

		clock-names = "gcc_gpu_memnoc_gfx",
			"gcc_gpu_snoc_dvm_gfx",
			"gpu_cc_ahb", "smmu_vote";

		qcom,secure_align_mask = <0xfff>;
		qcom,retention;
		qcom,hyp_secure_alloc;

		gfx3d_user: gfx3d_user {
			compatible = "qcom,smmu-kgsl-cb";
			label = "gfx3d_user";
			iommus = <&kgsl_smmu 0x0 0x401>;
			qcom,iommu-dma = "disabled";
			qcom,gpu-offset = <0xa8000>;
		};

		gfx3d_secure: gfx3d_secure {
			compatible = "qcom,smmu-kgsl-cb";
			label = "gfx3d_secure";
			iommus = <&kgsl_smmu 0x2 0x400>;
			qcom,iommu-dma = "disabled";
		};
	};

	gmu: qcom,gmu@3d6a000 {
		label = "kgsl-gmu";
		compatible = "qcom,gpu-gmu";

		reg = <0x3d6a000 0x30000>,
			<0xb290000 0x10000>,
			<0xb490000 0x10000>;
		reg-names = "kgsl_gmu_reg",
			"kgsl_gmu_pdc_cfg",
			"kgsl_gmu_pdc_seq";

		interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
				<0 305 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";

		qcom,msm-bus,name = "cnoc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<26 10036 0 0>,		/* CNOC off */
			<26 10036 0 100>;	/* CNOC on */

		regulator-names = "vddcx", "vdd";
		vddcx-supply = <&gpu_cx_gdsc>;
		vdd-supply = <&gpu_gx_gdsc>;

		clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
				<&gpucc GPU_CC_CXO_CLK>,
				<&gcc GCC_DDRSS_GPU_AXI_CLK>,
				<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
				<&gpucc GPU_CC_AHB_CLK>,
				<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;

		clock-names = "gmu_clk", "cxo_clk", "axi_clk",
				"memnoc_clk", "gpu_cc_ahb", "smmu_vote";

		/* AOP mailbox for sending ACD enable and disable messages */
		mboxes = <&qmp_aop 0>;
		mbox-names = "aop";

		gmu_user: gmu_user {
			compatible = "qcom,smmu-gmu-user-cb";
			iommus = <&kgsl_smmu 0x4 0x400>;
			qcom,iommu-dma = "disabled";
		};

		gmu_kernel: gmu_kernel {
			compatible = "qcom,smmu-gmu-kernel-cb";
			iommus = <&kgsl_smmu 0x5 0x400>;
			qcom,iommu-dma = "disabled";
		};
	};
};
